SS30 Floppy Disk Controller DC5

Board Photo (JPG 66K)

Board Photo High
Resolution (JPG 256K)

The DC5 Floppy Disk Controller is an all-new design for the Southwest
Technical Products Corp. 6800 and 6809 computers. It plugs into the SS-30 I/O
bus and fully emulates the SWTPC DC4 controller
and clones.
It supports double-sided, double-density disk for both 5.25-inch and 3.5-inch
floppy drives. The DC5 will boot and run all SWTPC Disk Operating Systems (that
were designed for the DC1 to DC4 controllers). The board will fit into the
original SWTPC 6800 case or the later cases that had openings in the back like
the S/09.

This new design uses a WD2797 that is a super set of the WD1797 and WD1691
chips that were used on the DC4. The earlier SWTPC controllers (DC1, DC2 and
DC3) used the Western Digital FD1771 FDC chip that only supported single-density
disks. The board was designed so that FD1771 chips could be used with a few cuts
and jumpers.

A Programmable Logic Device was used to reduce chip count and make the
printed circuit board, PCB, layout easier. A Xilinx XC9572 CPLD was chosen
because the development tools are free, the chip is low cost and it is easily
programmed in circuit. The design only uses about half of the XC9572 resources
so additional features can be added in the future.

More information about SWTPC computers can be found here. The FLEX User's Group has documention on
the FLEX disk operating system for the 6800 amd 6809.

DC5 Users
Guide Rev 2a (PDF 239K) (Revised April 29,
2003)

Schematic
single page 11 x 17 (PDF 113K) (Revised March 20,
2003)

Schematic 3
pages 8.5 x 11 (PDF 154K) (Revised March 20,
2003)

Schematic page 1
(PDF 63K)

Schematic page 2
(PDF 72K)

Schematic page 3
(PDF 22K)

Parts List
(PDF 7K)

Printed Circuit Board
layout (PDF 83K)

TMS2797 /
WD2797 Data Sheet (PDF 335K).

The control logic has been compressed into a single Programmable Logic
Device. A Xilinx 9572 CPLD was chosen because the development tools are free and
it is easily programmed in circuit. The chip is available from Digi-Key for
about $6. The CPLD was used to reduce chip count and make the printed circuit
board layout easier.

This revision was done in Verilog using Xilinx WebPACK 4.1 software.

DC5 CPLD
Functional Block Diagram (PDF 10K)

DC5
Design Description (PDF 419K)

Verilog Logic Design -
(ZIP 36K)

Michael
Holley's SWTPC Collection Home Page